* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
*.

Pin name A0 to A13 A10 (AP) BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 /RESET Par_In* 2 2 www.DataSheet4U.com Function Address input R.

EBE21AD4AGFA

EBE21AD4AJFA

EBE21AE8ACFA

EBE21AE8ACWA

EBE21EE8ABFA

EBE21EE8ACFA

EBE21EE8ACWA

EBE21FD4AGFD

EBE21FD4AGFN

EBE21FD4AHFE

EBE21FD4AHFL

EBE21FD4AHFT

EBE21FD4AJFT